Operating Voltage: 2.4V ~ 5.5V

Operating Temperature: -40 ~ 85℃

Package:

SC92F7352Q20R（QFN20）

SC92F7352X20U（TSSOP20）

SC92F7352M20U（SOP20）

SC92F7352N20U（NSOP20）

Core: 1T 8051

Flash ROM: 8K bytes Flash ROM (MOVC prohibited addressing 0000H ~ 00FFH) can be rewritten for 10, 000 times

IAP: Code option into 0K, 0.5K, 1K or 8K

EEPROM: independent 128 bytes EEPROM can be rewritten for 100,000 times. The data written-in has more than 10-year preservation life.

SRAM: Internal 256 bytes

System Clock (f_SYS):

l  Built-in high-frequency 24MHz oscillator (f_HRC)

l  As the system clock source, f_SYS can be set to 24MHz (3.7-5.5V), 12/6/2MHz (2.4-5.5V) by programmer selection.

l  Frequency Error: Suitable for （4.0V ~ 5.5V ）and（ -20 ~ 85℃ ）application environment, no more than ±1% of frequency error

Built-in Low-Frequency 128 kHz Oscillator (LRC):

l  Clock source of Base Timer (BTM), which can wake up the SC92F735X from stop mode

l  Clock source of Watch Dog Timer (WDT)

l  Frequency Error:  Suitable for 2.9V ~ 5.5V and -20 ~ 85℃ application environment, no more than ±4% of frequency error

Low-voltage Reset (LVR):

l  4-level LVR voltage options: 4.3V, 3.7V, 2.9V, 2.3V

l  The default is the Code Option value selected by the user

Flash Programming interface:

l  2-wire JTAG programming  interface

Interruption (INT):

l  9 interrupt sources: Timer0, Timer1, Timer2, INT0, INT2, ADC, PWM, UART and Base Timer.

l  2 external interrupt vectors shared by 6 interrupt ports, all of which can be defined in rising-edge, falling-edge or dual-edge trigger mode.

l  Two-level interrupt priority capability

Digital Peripheral:

l  Up to 18 bidirectional independently controllable I/O interfaces, able to configure pull-high resistor independently

l  P0/P2 ports with 4-level drive capability

l  All I/Os equipped with sink current drive capability (47 mA)

l  11-bit WDT with optional clock division ratio

l  3 standard 80C51 Timer/Counters: Timer0, Timer1 and Timer2

l   Six 8-bit PWM output channels with variable period and individual duty cycle

l   5 I/Os as output of the 1/2-bias LCD COM

l  1 independent communication interface: UART

Analog Peripheral:

l  9-channel 12-bit ±2LSB ADC

n  Built-in 2.4V reference voltage

n  2 options for ADC reference voltage: V_DD and internal 2.4V

n  Internal one-channel ADC, where VDD can be measured directly

n  ADC conversion completion interrupt

Power Saving Mode:

l  IDLE Mode: can be woken up by any interrupt.

l  STOP Mode: can be woken up by INT0 , INT2 and Base Timer