Operating Voltage: 2.4V ~ 5.5V

Operating Temperature: -40 ~ 85℃

Package:

SC92F7445B (LQFP32)

Core: Ultra-speed 1T 8051

Flash ROM: 16 Kbytes Flash ROM (MOVC prohibited addressing 0000H~00FFH 256 bytes)

IAP: Code option into 0K, 0.5K, 1K or 16K

EEPROM: 128 bytes EEPROM can be rewritten 100,000 times. The data written-in has more than 10-year preservation life.

SRAM: Internal 256 bytes + external 768 bytes + PWM&LCD RAM 44 bytes

System Clock (f_SYS):

l  Built-in 16 MHz high-speed RC oscillator (f_HRC):

l  IC system clock can be set by the programmer as

n  16 MHz @2.9~5.5V

n  8/4/1.33 MHz@2.4~5.5V

l  Frequency Error: Suitable for 3.0V ~ 5.5V and -20 ~ 85℃ application environment, no more than ±1%

Built-in Low-speed Crystal Oscillator Circuit:

l  Available to externally connect 32K oscillator as Base Timer clock source, able to wake up STOP

Built-in 128 kHz LRC Low-speed Oscillator:

l  Available to act as clock source of Base Timer (BTM) and WDT, which can wake up STOP

l  Frequency Error: 4.0V ~ 5.5V and -20 ~ 85℃ application environment, no more than ±4% of frequency error after register correction

Low-voltage Reset (LVR):

l  4-level LVR voltage options: 4.3V, 3.7V, 2.9V, 2.3V

l  The default is the Code Option value selected by the user

Flash Programming and Emulation:

l  2-wire JTAG programming and emulation interface

l  JTAG mode and Normal mode can be set through code option

Interruption (INT):

l  Totally 12 interrupt sources, including Timer0, Timer1, Timer2, INT0~2, ADC, PWM, UART, SSI, Base Timer, and CMP

l  Three external interrupt vectors shared by 16 external interrupt I/Os, which can be defined in rising-edge, falling-edge or double-edge trigger mode.

l  Two-level interrupt priority capability

Digital Peripheral:

l  Up to 30 two-way independently controllable I/O interfaces, able to configure pull-high resistor independently

l  P0~P3 (P3.0/1/2/3) 4-level control drive capability

l  All IOs equipped with sink current drive capability (50mA)

l  11-bit WDT, optional clock division ratio

l  3 standard 80C51 timers: Timer0, Timer1 and Timer 2

l  Eight 12-bit PWM output channels with variable period and individual duty cycle

l  1 independent UART communication port

l  1 UART/SPI/IIC communication interface (SSI)

l  16 * 16-bit hardware Multiplier-Divide Unit (MDU)

Analog Peripheral:

l  12-channel 12-bit ±2LSB ADC

n  12-channel 12-bit ±2LSB ADC

l  Built-in 2.4V reference voltage

n  2 options for ADC reference voltage: VDD and internal 2.4V

n  Internal one-channel ADC, where VDD can be measured directly

n  ADC conversion completion interrupt

l  1 analog comparator

n  4-channel input and 1-channel reference voltage input

n  16-level optional comparison voltage

Power Saving Mode:

l  IDLE Mode: can be woken up by any interrupt.

l  STOP Mode: can be woken up by INT0 ~ 2、and Base Timer.